The evolution of integrated circuit technology continues to increase transistor speed. At high switching frequencies, capacitive loading and coupling parasitics significantly degrade the speed and quality of signals in an integrated circuit. These effects are especially pronounced for those signals that are generated external to the integrated circuit. In other words, those signals that must travel from a printed circuit board, through an integrated circuit package, and into the integrated circuit. This path includes the following elements: a package pin of a printed circuit board component, a printed circuit board signal trace, an integrated circuit package pin, one or more vias, a signal trace or power plane, a package bond pad, a bond wire, and an integrated circuit bond pad. Each of these elements contributes some parasitic resistance, capacitance, and inductance to the signal path.
The parasitic resistance, capacitance, and inductance of the signal path can seriously compromise the quality of signals processed by sensitive integrated elements. As a result, the operation of the entire integrated circuit can be compromised.
The significance of this problem is especially appreciated in the context of a phase-locked loop. A phase-locked loop produces a recovered data or clock signal corresponding to an input reference signal. In the context of an integrated circuit, a phase-locked loop is commonly used to produce a recovered system clock signal that is used to govern the operation of the entire integrated circuit.
A phase-locked loop generally includes a phase comparator that is used in conjunction with a charge pump circuit to provide a pulsed error signal indicative of the phase difference between the reference signal and the recovered signal. The charge supplied by the error signal is used to develop a control voltage across a capacitor. A voltage controlled oscillator operates to vary the frequency of the recovered signal in accordance with the control voltage of the capacitor. Thus, it can be appreciated that when the capacitor of a phase-locked loop receives a degraded signal attributable to parasitic resistance, capacitance, and inductance of a signal path, the operation of the system clock can be compromised.
It would be highly desirable to provide a semiconductor package with an on-board storage capacitor for improved signal quality for sensitive integrated circuit elements, such as a voltage controlled oscillator of a phase-locked loop. It would also be highly desirable to exploit mature assembly processes in constructing such a package.